Dynamic Random Access Memories ("DRAMs") with dual ports first became popular in the mid 1980s. Armed with an additional port to allow for serial input/output access, these devices have been also labeled Video Random Access Memories ("VRAMs") because of their ability to overcome the bottleneck that existed in presenting data to and from the computer screen.
Referring to FIG. 1, an early conventional VRAM design is illustrated. Each VRAM comprises a memory array 10 having a number of memory cells, the number of cells being defined by the number of rows and number of columns in array 10. For example, a 1 megabit array would have 1024 rows and 1024 columns or some combination thereof. Coupled to each cell of array 10 is a random access memory port 20, as in traditional DRAM architecture. Random access memory port 20 allows for the selective access of each cell within array 10. Thus, any cell can be read or written through memory port 20.
To enable a block of stored data to be rapidly accessed, each row from array 10 is coupled to a bidirectional serial access port 30. This serial access port 30, also referred to as a Serial Access Memory ("SAM"), has a number of lines 35 directly corresponding to the number of columns of array 10. As such, using this configuration, a one-to-one relationship exists between the number of columns and the length of SAM 30.
The dual port DRAM design is particularly convenient for video applications because some address sequences, such as pixels in a raster scan, are predetermined. SAM 30 provides a means for reading a row of information from array 10 and serially outputting this data according to a particular scheme. Similarly, a row of information can be serially input to SAM 30, and subsequently written as a unit to the appropriate row of cells within array 10. As such, data may be read from the SAM at DRAM address speeds and serially output through the serial access port, and vice versa. Nonetheless, both a read and a write function of SAM 30 cannot be performed simultaneously.
In order to increase the overall speed of the dual port DRAM (VRAM) design, several architectural alternatives have been examined. One such configuration, corresponding to U.S. Pat. No. 4,891,794 is simply depicted in FIG. 2. Here, inventors Hush et al. employ a second independent bidirectional SAM, SAM-B 40, in addition to the SAM-A 30 of the original VRAM architecture. Like SAM-A 30, SAM-B 40 is independently coupled to each column of array 10, thereby enabling concurrent serial reading from one SAM and serial writing to a second SAM.
The additional SAM has particular advantages in the areas of image acquisition ("frame grabbers") and high speed network controlling and buffering. Without a second SAM, many of these designs must switch the direction of the serial port for input and output. For example, frame grabber video boards acquire images in real time and subsequently manipulate the image data, through filtering, edge detection, etc., or add computer generated information to the captured image, such as text overlay or windows. The composite image can then be output for display purposes. However, all three operations--input, output and processing--cannot be performed simultaneously in real time in a standard VRAM or DRAM. Thus, by adding the second serial access port or SAM, data can be input serially, serially output and displayed, and processed by means of the random access port, all at the same time. This is because all three ports--the random access port and both serial access ports--operate independently and asynchronously of each other, except during an internal transfer of data.
While the design of Hush et al. in U.S. Pat. No. 4,891,794 reaps the benefits of a three port random access memory, it also has several limitations. First, the need to couple each column of array 10 to each line of both SAM-A 30 and SAM-B 40 causes the layout of this circuit to be considerably more sizable than a conventional dual port DRAM architecture. Lines 45 must cross over or under SAM-A for proper coupling with SAM-B. In order to avoid this type of arrangement, circuit designers have repositioned the SAMs, locating one on each side of the memory array as well as divided the array into two equivalent halves.
Moreover, the triple port approach of Hush et al. in U.S. Pat. No. 4,891,794 is limited in terms of its ability to manipulate data serially. The design, though an improvement over the dual port DRAM approach, can serially read and serially write information only from two ports. There is a demand for a greater number of serial ports without substantially increased die size. Further, an enhanced overall speed is substantially needed with the onset of more advanced electronics. These demands are evident in communications applications of VRAM devices.
In large memory devices, connecting lines that run comparatively long distances on the die exhibit comparatively large capacitance and therefore are unacceptable for low power, high speed devices. As the demand for memory circuits having ever larger numbers of storage cells increases, memory device designers conventionally arrange memory array circuits in multiple sections, i.e. partitioned subsystems, called subarrays. Each such subarray conventionally includes a portion of the memory array as well as local decoding, sensing, and switching circuits that operate in parallel with other similar circuits in other subarrays. Though logically redundant, these local circuits avoid the need for long interconnections for high speed signaling. However, memory device architectures that employ considerable local circuitry suffer from lack of die surface area for additional and larger subarrays, consume too much power for important applications including battery powered and portable devices, and suffer from disadvantages associated with long interconnecting lines between circuit elements.
In view of the problems described above and related problems that consequently become apparent to those skilled in the applicable arts, the need remains in memory devices for an improved multi-port memory device.